POLY 411 |
| Semiconductor technology has historically followed a trend described by Moore's Law, which predicts that the number of transistors on a chip will double every 18 months, due to continued scaling of the devices, clever circuit design and larger chip sizes. While efforts to shrink the transistor continue, features of the devices are already approaching the atomic level. Currently, revolutionary and innovative technologies such as strained silicon, silicon-on-insulator, copper wiring and low-dielectric constant insulating materials are required to maintain the expected performance enhancements at these dimensions. Future generations of chips, which contain 10,000 meters of copper wiring and 200-500 million silicon transistors, will require dielectric constants below 2.0 to realize the full benefits of the reduced feature sizes. We have recently developed nanoporous polymer films that will soon be used as insulators in these chips (i.e., a nanocomposite of an insulating material and air ( = 1.01) with pore sizes well below the smallest device features (~50Å or less required). Our nanoporous materials use distinctive pore generating polymers, which are exquisitely designed to produce the requisite nanophase morphologies when mixed with thermosetting resins. In the future, as lithography costs continue to escalate, new methods of building multilevel thin-film structures will be needed. These are likely to involve aspects of soft-lithography, self-assembly and bio-inspired recognition. Similarly, new strategies will be required for future storage devices. |
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Industrial Sponsors Award in Honor of James Hedrick
1:30 PM-5:35 PM, Tuesday, 12 September 2006 San Francisco Marriott -- Salon B2, Oral
Division of Polymer Chemistry |